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High Throughput and Avalanched AES Encryption Method using Modified S-Box Architecture

Author(s):

Archana Senpuriya , SRIT, Jabalpur, MP, India; Prof. Divyanshu Rao, SRIT, Jabalpur, MP, India

Keywords:

AES, DES, Block cipher, S-Box, Mix-Column, Encryption, VHDL, FPGA

Abstract

The significance of the security problems is greater in current data networks than in earlier systems because users are provided with the way to accomplish very critical operations like banking transfer and sharing of confidential business data, which require very high levels of protection. Weak security architectures allow successful eavesdropping (unauthorised attack), message tampering and modification attacks to occur, with huge consequences for end companies, users and other departments. The Advance Encryption standard (AES) block encryption present at the core of the f8 data hiding algorithm and also the f9 data reconstructing algorithm for Universal data Telecommunications System networks. The design aim is to enhance the data conversion rate means the throughput to an appropriate value hence the design can be used as a cryptographic sub-processor in very high speedy network uses. The work is to design an optimised solution for secure data communication AES is the standard encryption technique but proposed work is more optimised solution for the same when the chip area and encryption time considers as design parameters. Thesis work describe a new method for the Sbox-8 AES substitution and Key gen approach.

Other Details

Paper ID: IJSRDV9I60071
Published in: Volume : 9, Issue : 6
Publication Date: 01/09/2021
Page(s): 163-168

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