An Implementation of a Compact 32-Bit Advanced Encryption Standard Design for Embedded Systems

� The need for security has been increasing day by day. Various algorithms for encryption and decryption have been proposed, but all are having some problem with them. So our objective is to propose high effective AES core hardware architecture for implementing a module to encrypt/decrypt the data that apply to FPGA platforms effectively in the terms of speed, scale size and power consumption. Recently, much research has been conducted for security of data transactions on embedded platforms. In this we describe a 32-bit architecture developed for Rijndael algorithm to accelerate execution on 32-bits platforms with reduced memory. A very low-cost implementation of around 700 occupied Slices is obtained under 347.515 MHz frequency. Verilog implementation of the proposal of the AES optimized algorithm is presented. A simulation campaign has been carried out, in order to evaluate time performances. We report the results of the AES optimized algorithm only in the case of a key size of 128 bits.