An Enhanced High Performance and Low Power FIR Low Pass Filter Based on Array Multiplier

Finite impulse response (FIR) filters are important building blocks for various digital signal processing (DSP) applications. Recently, because of the increasing demand for video-signal processing and transmission, high speed and high-order FIR filters have frequently been used to perform adaptive pulse shaping and signal equalization on the received data in real-time. Multiplication is a very important operation in many DSP applications. FIR filters are basic building blocks for various DSP applications. FIR contains 3 blocks adder, multiplier and delay elements. To achieve a high performance in the filter the thing is to concentrate on the type of adders, multipliers used in the FIR circuit. We performed it in different CMOS technology like 45, 90,180nm, and require 40.38% less area than the original FIR filter. Design is coded in Verilog HDL maintaining industry standard coding guidelines. Verification plan is developed describing simulation of design and synthesis strategy documented. Synthesis scripts were coded, design is synthesized on 45,90,180nm technology and timing checks performed. The details of synthesis is mentioned in the paper.