Combinational Logic Circuit Design for Low Power VLSI Application Using Majority Function

With the explosive growth in laptops, portable personal communication systems and the evolution of the shrinking technology low-power design can be addressed at different design levels, such as software, architectural, algorithmic, circuit, and process technology level . This paper presents an effective approach to reduce power consumption of any arbitrary combinational logic circuit by applying transformations at the logic level, whilst preserving the desired functionality. We have considered implementation with static CMOS logic style, due to its robustness against device and process variations. Simulation results obtained using a 0.180 micron TSMC CMOS technology for savings power by 25% over the best of existing methods; while considering spatio-temporal correlation in inputs, average power savings of 13.22 % was obtained. The proposed method also enabled overall improvement in worst case delay parameter by 26.52%, over the best of other methods.