Review of Design and Testing of Combinational Logic Circuits using Built in Self-Test Scheme for FPGAS |
Author(s): |
| Megha Tarole , IES College of Technology, Bhopal, India; Ashish Raghuwanshi, IES College of Technology, Bhopal, India |
Keywords: |
| LFSR (Linear Feedback Shift Register), PRPG (Pseudo Random Pattern Generator), MISR (Multiple Input Signature Register), Primitive Polynomial, Galois Field, BIST (Built in Self-Test) |
Abstract |
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Very Large Scale Integration (VLSI) has made a dramatic impact on the growth of integrated circuit technology. It has not only reduced the size and the cost but also increased the complexity of the circuits. The positive improvements have resulted in significant performance/cost advantages in VLSI systems. There are, however, potential problems which may retard the effective use and growth of future VLSI technology. Among these is the problem of circuit testing, which becomes increasingly difficult as the scale of integration grows. Because of the high device counts and limited input/output access that characterize VLSI circuits, conventional testing approaches are often ineffective and insufficient for VLSI circuits. |
Other Details |
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Paper ID: IJSRDV6I10170 Published in: Volume : 6, Issue : 1 Publication Date: 01/04/2018 Page(s): 347-349 |
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