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Semiconductor Memory Data Error Detection and Correction using Decimal Matrix Code

Author(s):

Meenakshi Gupta , Acropolis Institute of technology & Research Indore

Keywords:

Decimal Addition, Error Correction Codes (ECCs), Error Syndrome, Hardware Memory, Multiple Cell Upsets (MCUs)

Abstract

In Multiple cells upsets (MCUs)is an important issue in the reliability of memories exposed to radiation environment transient. There are number of technique available to protect the memory data from radiations and transient. However, protection from a limited variation of radiations is provided by particular packaging. Nowadays in the field of wireless communication for the number of application the devices are exposed to a very wide range of environment radiations. So for authenticating the data before it is processed several additional data preservation techniques are always preferred. Error correction codes (ECCs) are one of the common techniques for encoded data and that encoded data is to be stored in memories. An error correction code is always preferred for implementation because that requires minimized delay overhead in data correction and a less number of redundant bits to be stored. In this paper the implementation is based on FPGA for memory data error detection and correction code that involves simple decimal addition algorithm in the encoding of data that is to be stored in memory. Hamming Code is preferred for decoding of the data for error detection and correction. This technique used a divide-symbol concept to represent the linear data in groups to make symbolic code and the length of the symbol is inversely proportional to the delay overhead of the code.

Other Details

Paper ID: IJSRDV4I100261
Published in: Volume : 4, Issue : 10
Publication Date: 01/01/2017
Page(s): 606-609

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