Design of the Physical Layer of PCI Express Using VHDL |
Author(s): |
| Priyanka M. Zade , G H Raisoni Academy of Engineering and Technology, Nagpur, Maharashtra, India; Dr. Sanjay L. Haridas, G H Raisoni Academy of Engineering and Technology,Nagpur, Maharashtra, India; Shubhangini Ugale, G H Raisoni Academy of Engineering and Technology, Nagpur, Maharashtra, India |
Keywords: |
| PCI Express, Physical Layer, VHDL Code |
Abstract |
|
PCI Express (PCIe) is the newest name for the technology formerly known as 3GIO. . It is used as a High speed communication protocol for connecting among different devices. According to PCI Express 1.0a, this paper presents the physical layer architecture. It uses packet data for reliable communication to transport the data from transmitter to receiver side. The paper presents the reliable conveying of data, with the addition of start and end bit to each TLPs and DLLPs in the transmit side, and how the packets are processed on the receiver side. The simulation is performed using Xilinx ISE 9.1 Software and coding is done using Very High Speed Integrated Circuit Hardware Description Language (VHDL). |
Other Details |
|
Paper ID: IJSRDV3I50152 Published in: Volume : 3, Issue : 5 Publication Date: 01/08/2015 Page(s): 121-124 |
Article Preview |
|
|
|
|
