Design of 64 Bit MAC Unit for Efficiency Improvement using Vedic Multiplier |
Author(s): |
| Sumit C. Katkar , GHRAET, NAGPUR, MAHARASHTRA; Pragati Kene, GHRAET, NAGPUR, MAHARASHTRA; Shubhangini Ugale, GHRAET, NAGPUR, MAHARASHTRA |
Keywords: |
| MAC, Vedic Multiplier, VHDL, Ripple Carry (RC) Adder, Carry Look Ahead Adder |
Abstract |
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Multiplier Accumulator Unit (MAC) is a part of Digital Signal Processors. The MAC unit speed depends on the speed of multiplier. The proposed MAC unit reduces the area by reducing the number of multiplication and addition in the multiplier unit. Increase in the speed of operation is achieved by the nature of the Vedic multiplier unit. So by using an efficient Vedic multiplier in terms of speed, power and area, the performance of MAC can be increased. For this fast method of multiplication based on ancient Indian Vedic mathematics is used. Among various method of multiplication in Vedic mathematics, Urdhva Tiryagbhyam is used and the multiplication is for 64 X 64 bits. Urdhva Tiryagbhyam is a general multiplication formula applicable to all cases of multiplication. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros. |
Other Details |
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Paper ID: IJSRDV3I50150 Published in: Volume : 3, Issue : 5 Publication Date: 01/08/2015 Page(s): 131-134 |
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