Design of IEEE 754 Format 32 Bit Complex Floating Point Vedic Multiplier |
Author(s): |
| Suvina Vinayan , GHRAET, RTMN University; Pro. Anup R. Nage, GHRAET, RTMN University |
Keywords: |
| Complex Floating Point Numbers, Urdhva Tiryagbhyam, Vedic Mathematics, IEEE 754 |
Abstract |
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this paper proposes a design for a multiplier which can calculate complex floating point numbers of 32 bits using Vedic multiplication method. For multiplication, the Urdhva Tiryagbhyam sūtra from Vedic mathematics is applied. The use of the Vedic mathematics and their application to the multiplier make certain significant reduction of propagation delay, successively improves speed. The design can handle underflow and overflow cases. The inputs to the multiplier are provided in IEEE 754, 32 bit binary format. |
Other Details |
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Paper ID: IJSRDV3I50098 Published in: Volume : 3, Issue : 5 Publication Date: 01/08/2015 Page(s): 128-130 |
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