An Improved Systematic Error Correcting Code for Low Power and Low Complexity in Chip |
Author(s): |
| E.Yamini , SRI ESHWAR COLLEGE OF ENGINEERING; R.Uthira devi, SRI ESHWAR COLLEGE OF ENGINEERING; N.Ragavi, SRI ESHWAR COLLEGE OF ENGINEERING; S.Sharmila Devi, Oracle |
Keywords: |
| Low Power and Low Complexity in Chip, Systematic Error Correcting Code |
Abstract |
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An error-correcting code is an algorithm for expressing a sequence of numbers such that any errors which are introduced can be detected and corrected based on the remaining numbers.The Convolution code helps to improve the error performance or reduce the power consumption.The stored data is protected with error-correcting codes (ECC) for reliability reason.This method is proposed to improve the latency for information encoded with ECC. Therefore the chip area and power is reduced by the Convolution code.The proposed code examines whether the incoming data matches the stored data if a certain number of erroneous bits are detected and corrected for more than two bit. |
Other Details |
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Paper ID: IJSRDV3I2380 Published in: Volume : 3, Issue : 2 Publication Date: 01/05/2015 Page(s): 2386-2389 |
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