Design and Analysis of Low Power Pulse Triggered Flip flop Based on Single Feed-Through Scheme A Review |
Author(s): |
| anuka , IIET, Kinana, JIND; Shelly Garg, IIET, Kinana, JIND |
Keywords: |
| Flip-Flop (FF), Low Power, Pulse- Triggered |
Abstract |
|
In this present work, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock (TSPC) latch based on a signal feed-through scheme a review is presented. Proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered flip-flop (P-FF) designs and achieves better speed and power performance. On the bases of post-layout simulation results using CMOS 90-nm technology, the signal feed-through design (SFTD) outperforms the conventional pulse flip-flop (FF) design data-close-to-output (ep-DCO) by 8.2% in data-to- Q delay. In the meantime, the performance edges on power- delay-product (PDP) and power metrics are 22.7% and 29.7%, respectively. |
Other Details |
|
Paper ID: IJSRDV3I2136 Published in: Volume : 3, Issue : 2 Publication Date: 01/05/2015 Page(s): 333-336 |
Article Preview |
|
|
|
|
