A Low Power Row and Column Compression for High-Performance Multiplication on FPGAs using Fast Adder

Digital system design in a remarkable and emerging field now days. Users are using digital devices for almost each and everything in daily life like calculator for calculation, Digital cameras for photo shot and video recording, Mobiles for communication, Computer to connect all over the world etc. In fact, increasing demand for manageable digital electronics products for computing and communication, as well as for other applications, has necessitated longer battery life, lower weight, high speed and lower power consumption. However, the two design criteria are often in conflict by improving one particular aspect of the design constrains the other. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. In majority of digital signal processing (DSP) applications, multiplication and accumulation are the most critical operations.