Read/Write Analysis of FinFET based 8T SRAM using 22nm gate length

CMOS devices are scaling down to nano ranges resulting in increased process variations and short channel effects which not only affect the reliability of the device but also performance expectations. The SRAM design uses the smallest transistors possible and is also susceptible to reliability issues and process variations, making it an ideal benchmark circuit to compare technologies . Low power static-random access memories (SRAM) have become a critical component in modern VLSI systems. They occupy a large portion of area and accounts for a major component of power consumption in today’s VLSI circuits. In this paper, new SRAM design for FinFET technology are proposed. The FinFET has very good candidate for future VLSI due to its simple architecture and better performance when compare to SOI MOSFET . FinFET based SRAM has been proposed as an alternative solution to the bulk device. FinFET has better scalability and better short channel effect. In this paper a study of designing and writting operation of 8T finfet SRAM using Visual TCAD tool . The high-k dielectric material is replace to dielectric.the analysis of 8T FinFET SRAM at 12nm gate length and at low supply voltage at 0.8 v.