An Efficient Design of Parallel Prefix Adder Using Majority Gates (MG)

Moore’s law states that the number of transistors that could be integrated into a single die would grow exponentially with time. Thus this causes increasing computational complexity of the chip and physical limitations of devices such as power consumption, interconnect will become very difficult. According to recent analysis the minimum limit for transistor size may be reached. Thus, it may not be possible to continue the rule of Moore’s law and doubling the clock rate for every three years. So in order to overcome this physical limit of CMOS-VLSI design an alternative approach is Quantum dot Cellular Automata (QCA). Among various circuits adder plays a vital role in digital devices. In this survey a binary adder is taken for analysis and a new adder is designed based upon QCA technology. The aim of this proposed technique is that to reducing number of majority gates used in the design. This will lead to reduce number of QCA cells so that total area of adder circuit can be minimized compare to previous designs. It also achieves reduced power consumption and high speed performances than all other existing QCA adders.