Design & Implementation of LUT Based Multiplier Using APCOMS Technique

The multiplication is major arithmetic operation in signal processing and in ALU's .The multiplier uses look-up-table (LUT) as memory for their computations. However, we do not find any significant work on LUT optimization for memory-based multiplication. A new approach to LUT design was presented, where only the odd multiple storage (OMS) scheme. In addition to that the antisymmetric product coding (APC) approach, the LUT size is reduced to half and provides a reduction. When APC approach is combined with the OMS technique, the two's complement operations could be simplified since the input address and LUT output could always be transformed into odd integers, and thus reduces the LUT size to one fourth of the conventional LUT. The proposed LUT multipliers for word size L=W=5 bits are coded in VHDL and synthesized in Xilinx 14.2. It is found that the proposed LUT-based multiplier involves comparable area and time complexity for a word size of 5-bits.