Design & Check Cyclic Redundancy Code using VERILOG HDL |
Author(s): |
| Prof. Dhiraj Jain , ITM Bhilwara, RTU, Rajsthan; Hiren G. Patel, ITM Bhilwara, RTU, Rajsthan |
Keywords: |
| Verilog HDL, CRC tools, PERL, RTL. |
Abstract |
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the CRC or cyclic redundancy check is a widely used technique for error checking in many protocols used in data transmission. The aim of this project is to design the CRC RTL generator or a tool that calculates the CRC equations for the given CRC polynomials and generates the Verilog RTL code .This block deals with the calculation of equations for standard polynomials like CRC-4, CRC-8, CRC-16, CRC-32 and CRC-48, CRC-64 and also user defined proprietary polynomial. To use PERL as the platform it also aims at having a simpler user interface. To generate the RTLs for any data width and for any standard polynomial or user defined polynomial, this design aims to be complete generic. The RTLs generated by this tool are verified by System Verilog constrained random testing to make it more robust and reliable. |
Other Details |
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Paper ID: IJSRDV1I5015 Published in: Volume : 1, Issue : 5 Publication Date: 01/08/2013 Page(s): 1096-1098 |
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