Efficient CA-Based Byte Error Correcting Codes using Parallel Processing

Cellular Automata (CA) is a tool used to generate byte error correcting code. CA-based byte Error Correcting Code (ECC) which overcomes the weaknesses and limitation of existing scheme. Proposed byte ECC scheme can correct errors when errors are distributed within information and check bytes or concentrated in any one of them. Cellular automata are already employed by several researchers for designing bit and byte error detecting and correcting codes. CA based VLSI design is more attractive because of its modular, regular and cascadable construction. RS codes are popularly used to detect and correct burst and as well as random errors in different communication systems and storage mediums. Simple and modular architecture of cellular automata based encoder and syndrome generator are proposed by employing the regular structure of cellular automata. Proposed design has been optimized using a parallel processing technique. In this work, a new decoding logic circuit has been introduced for error correction. Proposed encoder and syndrome generator circuits have less computation time compared to existing cellular automata based designs. All functional blocks are simulated and synthesized using FPGA based Xilinx ISE simulator.