Hybrid Matrix Code for Enhanced Memory Reliability against Multiple Cell upsets |
Author(s): |
Sunitha.K , Kalaignar Karunanidhi Institute of Technology; S.Maria Antony, Kalaignar Karunanidhi Institute of Technology |
Keywords: |
Soft Errors, Multiple Cell Upsets (MCU), Error Correction Codes (ECC), Memory, Decimal Matrix Code (DMC), Hybrid Matrix Code (HMC), Encoder Reuse Technique (ERT) |
Abstract |
The advancement in technologies results in reduction of transistor size which makes the devices more vulnerable to noise and radiation effect that causes soft errors. Soft errors or transient error occurs when radioactive atoms decay and release alpha particles into the chip. These alpha particles hit the memory cell and change its state value which affects memory reliability. Soft errors in Memories can cause multiple cell upsets (MCUs) around the location of strike. The memory cells can be protected against MCUs using various Error Correction Codes (ECCs). Decimal Matrix Code (DMC) is a type of ECC that has been recently proposed for memory protection. The main issue of using DMC is that it has more redundant bits and limited error correction capability compared to the proposed work. The Hybrid Matrix code (HMC) is a combination of Matrix Code and Hamming code along with Encoder Reuse technique (ERT) has been proposed to assure reliability in the presence of MCUs and reduces the redundant bits and it corrects more error compared to the existing method. ERT uses HMC encoder itself to be part of the decoder. The ERT is used to minimize the area overhead of extra circuits without disturbing the whole encoding and decoding process. The proposed algorithm is coded in VHDL and simulated using ModelSim and Xilinx ISE 8.1i Simulator. The results obtained show reduced area usage, delay overhead and redundant bits compared to existing method. |
Other Details |
Paper ID: IJSRDV3I1023 Published in: Volume : 3, Issue : 1 Publication Date: 01/04/2015 Page(s): 114-117 |
Article Preview |
|
|