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FPGA Implementation of Mixed Radix CORDIC FFT


IZHAR ANSAR AHMED , M.E. Scholar, Electrical & Electronics Engineering, Department of PG Studies, PRMCEAM, Badnera, Amravati; Dr. M. S. ALI, PRINCIPAL AND PROFESSOR, PRMCEAM, BADNERA, AMRAVATI




In this Paper, the architecture and FPGA implementation of a Coordinate Rotation Digital Computer (CORDIC) pipeline Fast Fourier Transform (FFT) processor is presented. Fast Fourier Transforms (FFT) is highly efficient algorithm which uses Divide and Conquer approach for speedy calculation of Discrete Fourier transform (DFT) to obtain the frequency spectrum. CORDIC algorithm which is hardware efficient and avoids the use of conventional multiplication and accumulation (MAC) units but evaluates the trigonometric functions by the rotation of a complex vector by means of only add and shift operations. We have developed Fixed point FFT processors using VHDL language for implementation on Field Programmable Gate Array. A Mixed Radix 8 point DIF FFT/IFFT architecture with CORDIC Twiddle factor generation unit with use of pipeline implementation FFT processor has been developed using Xilinx XC3S500E Spartan-3E FPGA and simulated with maximum frequency of 157.359 MHz for 16 bit length 8 point FFT. Results show that the processor uses less number of LUTs and achieves Maximum Frequency.

Other Details

Paper ID: IJSRDV3I100293
Published in: Volume : 3, Issue : 10
Publication Date: 01/01/2016
Page(s): 566-570

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