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Design of Low Power, High Speed 3-Bit Pipelined ADC

Author(s):

Prof. H. G. Bhatt , LDRP- ITR; Vaishali Doctor, LDRP- ITR

Keywords:

Sample & Hold, Comparator, Buffer, Reference Voltage Generator, Subtractor cum amplifier, Switch

Abstract

The design of high speed, lower power A/D converter architectures have been investigated and can be found in several applications. The low power techniques used in this design include the dynamic comparators and capacitor scaling which are made possible with this architectural selection. To be compatible with the digital integrated circuit now running at 3.3V power supply, some techniques for low supply voltage are introduced, which include a 3.3V Op Amp and low voltage SC circuits. In order to reduce the power even more, one can reduce the per-stage resolution and cascade more stages to get the full resolution. This particular architecture is called the Pipelined architecture, mainly because the analog input signal is passed through a pipeline of flash A/D (sub-ADC) and interstate gain blocks. The advantage of this architecture is its reduced complexity. With a given per-stage resolution, an A/D converter of a given resolution can be achieved by cascading an appropriate number of identical pipelined stages. In any A/D converters, some reference voltages are generally required to set a reference for the sampled input to be compared to. Tspice simulation results & Layout using 1.2μm CMOS Technology parameters for the proposed design of Low Power - Low Voltage 3 bit Pipelined ADC are discussed.

Other Details

Paper ID: IJSRDV1I4036
Published in: Volume : 1, Issue : 4
Publication Date: 01/07/2013
Page(s): 962-966

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